The present invention relates to a resource management device for arbitrating access requests issued from respective masters to at least one shared resource in a system.
In system LSI, a plurality of masters, such as a microprocessor, a DSP (Digital Signal Processor) and a DMA (Direct Memory Access) controller, access a shared resource such as a memory or a peripheral I/O (input/output) controller. This configuration needs a resource management device for efficiently arbitrating access requests from the respective masters to the shared resource.
According to a conventional technique, based on priority order information on the maters held in the form of a table, the resource management device arbitrates access requests at regular timings. A plurality of patterns of priority order information are stored in this table so that the patterns are sequentially switched from one to another at regular timings of arbitration. Each of the masters is allowed to gain access permission a number of times corresponding to the number of times the master is assigned the highest priority in the priority order patterns. Accordingly, the minimum access bandwidth for each master is guaranteed (see, US 2004/0073730 A1).
As described above, in a system in which a master having the highest priority is previously determined at each arbitration timing, a problem arises when access requests are issued unevenly with respect to time. For example, when a master which is assigned the highest priority at regular arbitration timings in one cycle issues access requests mainly in the first half of this cycle, a desired access bandwidth is not guaranteed for the master, causing a decrease in access efficiency. This is because the arbitration timings assigned the highest priority do not coincide with all the timings of issuing access requests.
If the masters issue access requests at irregular timings, it is difficult to previously determine a master assigned the highest priority at each arbitration timing so as to avoid the decease in access efficiency.